Last year, SiFive introduced their first RISC-V cores competing with Arm Cortex-R family of processors thanks to their S7 Series 64-bit RISC-V Core IP providing an answer to Arm Cortex-R7/R8 32-bit real-time processors.
The company has now announced the SiFive S2 RISC-V core that it claims to be the world’s smallest 64-bit embedded core, and also the first SiFive IP core without any direct competitive equivalent in the market.
For now, there’s only one core in the family with SiFive S21 offering the following key features:
- RISC-V ISA – RV64IMAC
- 64-bit AXI Ports
- Machine and User Mode with 4 Region Physical Memory Protection
- 3-stage pipeline with Simultaneous Instruction and Data Access
- 2 Banks of Tightly Integrated Memory (TIM)
- CLIC (Core Local Interrupt Controller) with 127 interrupts
- Advanced debug with 4 hardware breakpoints/watchpoints
- Performance – 1.6 DMIPS/MHz; 3.2 Coremarks/MHz
The company compares its to the SiFive S5 cores, which I had not heard about previously, and are competing with Arm Cortex-R4/R5 cores. SiFive S2 is just half the size of a similarly configured S5 core, and as such is particularly well suited for area constrained applications demanding a 64-bit processor.
That means S2 may be found in 64-bit Embedded Controllers, consumer applications, industrial automation, or integrated as a management core as part of a more complex SoC.